1. Field of the Invention
The present invention relates to a digital filter, more particularly to an oversampling digital filter which is used for a digital audio system.
2. Prior Art
The conventional digital signal processing circuit uses the system clock to thereby carry out the digital signal processing, wherein the system clock has the period which is obtained by dividing the input sampling period by the specific step number. Hereinafter, description will be given with respect to the digital filter (i.e., oversampling filter) as an example of the conventional digital signal processing circuit, wherein such digital filter is used in the digital audio device such as the compact disk (CD) player, broadcasting satellite (BS) receiver, digital audio tape recorder (DAT) etc.
In the digital filter, the input digital signal is resampled by the frequency which is N times (where N denotes the integral number) larger than the sampling frequency thereof, and then it is outputted. Thereafter, the digital signal having high sampling frequency which is outputted from the digital filter is subject to the digital-to-analog (D/A) conversion, by which it is possible to obtain the analog signal in which the audio signal band is sufficiently apart from the unnecessary higher harmonic band. Therefore, such unnecessary higher harmonics of the analog signal outputted from the D/A converter can be easily removed by the low-pass filter. Thus, it is possible to reproduce the audio signal having good quality.
FIGS. 13A, 13B are block diagrams showing the configuration of the audio signal reproducing circuit for the CD player which uses the conventional digital filter.
In FIG. 13A, 1 designates a signal processing circuit. As the integrated circuit (IC) of this circuit, "YM3623B" produced by YAMAHA Corporation is known, for example. The pit information read from the CD is digitized in the signal processing circuit 1. This signal processing circuit 1 outputs digital data SDI corresponding to the pit information by every predetermined sampling period FW=1/fs in serial manner. In addition, this circuit 1 also outputs bit clock BCI synchronizing with each bit data of SDI, and it further outputs word clock SDSY by every sampling period FW.
In addition, 2 designates a digital filter, whose IC is known as "YM3414" produced by YAMAHA Corporation, for example. This digital filter 2 inputs the digital data SDI from the signal processing circuit 1 by the timing corresponding to the bit clock BCI. Herein, the digital data SDI is configured by 16 bits as one word. Then, one word data for left (L) channel is fed to the digital filter 2 while the word clock SDSY is at "1". On the other hand, another word data for right (R) channel is fed to the digital filter 2 while SDSY is at "0". By detecting the change in the level of the word clock SDSY, the digital filter 2 detects the change-over point of the word length of SDSY. Thus, the digital filter 2 inputs the digital data SDI of one word for R channel and another SDI of one word for L channel.
As described above, the digital filter 2 inputs the digital data SDI by every sampling period FW. Thereafter, the digital filter 2 performs the arithmetic operation to thereby obtain the digital data corresponding to the sampling frequency 8 fs which is eight times larger than the input sampling frequency fs. Such digital data is sequentially and serially outputted as digital data DRO (for right channel), DLO (for left channel) by every frequency which is one-eight longer than the input sampling frequency FW. Then, the digital filter 2 outputs an output bit clock BCO synchronizing with each bit data of the digital data DRO, DLO, and it also outputs an output word clock WCO and a sample/hold signal SHL synchronizing with the timing when the digital data DRO, DLO are sent. This digital filter 2 provides an oscillator circuit 2X having an oscillation frequency which is around 400 fs. The output of this oscillator circuit 2X is subject to the phase synchronization so that the internal clock is generated. Based on this internal clock, several parts of the digital filter 2 operate. In other words, the processing of the digital filter 2 is performed with the signal processing circuit 1 in phase-synchronized manner.
In FIG. 13A, 3R, 3L designate digital-to-analog (D/A) converters each of which converts the digital data DRO, DLO from the digital filter 2 into analog signals. The digital data DRO, DLO are serially inputted into the D/A converters 3R, 3L by the bit clock BCO. At the changing point of the word clock WCO, the digital data is latched by an internal latch circuit (not shown) built in the D/A converter so that it is subject to the D/A conversion. Thus, the digital data DRO, DLO are converted into analog signals AR, AL, which are respectively fed to sample/hold circuits 4R, 4L. Therefore, these analog signals AR, AL are subject to the sample/hold operation, and then the unnecessary higher harmonics are removed from them by analog filters 5R, 5L. Finally, the analog filters 5R, 5L respectively output an audio signal RA for R channel and another audio signal LA for L channel.
Incidentally, the circuit shown in FIG. 13A can be partially modified as shown in FIG. 13B. More specifically, in FIG. 13B, a high speed clock Ca generated from the signal processing circuit 1 is supplied to an input terminal XI for oscillator circuit of the digital filter 2. By use of the configuration of FIG. 13B, it is also possible to configure the audio signal reproducing circuit having the same function of FIG. 13A.
In the above-mentioned conventional digital filter 2, its circuit design is made based on the input timing specifications such as the bit clock number (which is called as "bit clock rate") which is inputted by every input sampling frequency fs and by every sampling period FW. The sampling frequency fs of the digital signal varies depending on the system. For example, fs is at 32 kHz in the BS receiver, 44.1 kHz in the CD player and 48 kHz in the DAT. In addition, several kinds of bit clock rates are used, wherein the bit clock rate ranges from 32 fs to 192 fs, for example. Therefore, in order to design the digital audio system, it is necessary to prepare the specific digital filter corresponding to the input timing specifications. For this reason, there is a disadvantage in that the circuit design must be difficult. In the case where the desirable digital filter is not available, it is necessary to newly purchase or newly develop the desirable digital filter, which makes the cost for the system higher. Further, the conventional digital filter requires the high speed clock which corresponds to the signal processing circuit 1 in phase-synchronized manner. Accordingly, there is a problem in that the conventional digital filter requires the high interface technology.